Robert A. Proctor's Résumé

• DeVry Technical Institute, Chicago, Ill. - 1965
  AAS in Electronics Engineering Technology
• Newark College of Engineering, Newark, NJ - 1971
  BSEE with minor in Computer Science
  Eta Kappa Nu, Tau Beta Pi, Honors

• VLSI Chip Design; VLSI Chip Design Methodology; Chip Floorplanning
• Chip Design Tools: HLD/LDP, Cadence Preview, IBM ChipBench, Synopsys, Shapes Checking
• Platforms: RS/6000, SUN, VM, MVS
• Languages: perl, html, pascal, C, PL/1, REXX
• Documentation: Framemaker, Bookmaster, MS-Word
• Management Experience

Advisory Engineer, ASIC Products, IMD Essex Jct, VT

3/1994 - Present

• Responsible for ASIC Floorplanning strategy and support. Tools include High Level Design Systems Logic Design Planner, Cadence Preview, and IBM's HDP-Lite.
• Developed IOSpecify, a tool that simplifies specification of data related to VLSI Chip IO.
• Developed HLD/LDP Design Kit Builder.
• PD Methodology Team Leader.
• Rule Tool Design Kit Interlock Coorination.
• Design Kit Integration Testing for IBM's CMOS5 and CMOS6 technologies

• Responsible for Floorplanning tools and chip floorplanning for the Chancellors Chip set for mainframe computer products.
• Significant enhancements for methodology which used the Pepper floorplanner.

Advisory Engineer, DSD Kingston, NY

5/1989 - 9/1993

• TDP team leadership and project coordination.
• Application of the Pepper floorplanning tool to a family of Mainframe Computer chips.
• Liberty-S Process Documentation.
• H8 Testchip Generation With ELAPS: Led a three-person team and developed a methodology for connecting groups of Seneca chips into much larger Empire chips. This activity included installing ELAPS, a Rochester program, debug, programming, testing, coordination, etc.
• Wisdom Systems' "The Concept Modeller": Wrote the justification and solved many logistical problems for doing the evaluation.
• General Recruiting and PhD Recruiting.
• Area representative for the Electronics Design Automation / Iter-division Technical Liasion.

Advisory Engineer/Manager, DSD Kingston, NY Advanced Design Development

10/1987 - 5/1989

• Support for Timing Driven Placement (TDP) with focus on Cycle Time reduction, Automation of Release Distribution, Menu System GUI, User Manual and Bipolar support.
• Other responsibilities included Recruiting, Electrical-to-Logical Checking and area representative for the EDA/ITL.

Advisory Engineer/Manager, CPD Kingston, NY VLSI Tool Development

1985 - 10/1987

• Responsible for VLSI PD tool Development in a custom circuit design environment. Major activities included continuing support for VIM with Compacted Arrays, re-programming design tools for compatablity with XA architecture, KWIRE development and IDEA DataBase applications.
• Workscope related to transfer to RTP included staffing, VM, MVS and tool support plans and personnel coordination.

• Design Tool Automation for a department of VLSI and Circuit design engineers using a Motorola HMOS technology.
• Developed the Variable IMage (VIM) System. Applied VIM algorithms to Motorola HMOS, a single level metal technology and released several HMOS chips. Expanded VIM to support Toshiba CMOS technologies including 3-micron and 2-micron Gate Arrays with 550 to 10K circuits. Released over 70 chips without a defect related to the design system.

• Investigated automation techniques for custom chip design. This activity resulted in the fundamental ideas behind the VIM System. Task Force concluded by indicating significant productivity advantages were possible with the automation plan.

• Wrote programs for conversion of TUSKEN engine BDL/S into a Nodes file for testing the Yorktown Simulation Machine (YSE). Developed SIMEXEC exercise code to control simulation and simulate RAM. Developed methods to model simulation RAM in VM storage. Released my BDL/S loader to Boca Raton.

• Lead Engineer for 1 of the 4 TUSKEN chips.
• Physical Design Automation programming with emphasis on Macro Generation, routing, checking, and overall chip design. My MACASM-GL1GEN programs replaced the previously manual custom design of the 4-chip TUSKEN engine.

Staff Engineer, Poughkeepsie, NY Technology Mapping to LSI

1976 - 4/1981

• Maintained and enhanced the automatic macro generation, placement, wiring, GL/1 and BDL/S generation programs of the LDL Design System.
• Created methods to link Los Gatos, Poughkeepsie, and East Fishkill together with the IBM internal network.
• Print utility for careating the IBM Internal network map. Used the LDL tools to create the map as if it were a LSI chip.
• Set up a graphics lab with an IGS system and a Versa-Tech XY plotter. I led several programmers in projects to automate rule generation.
• Processed PD jobs for the first 13 engineering parts for MS-416, the masterslice used in Siearra, the 308X machines. Helped coordinate the switch to the EDS system for design of production parts.

Jr. Engineer, East Fishkill, Components Division NY Array Design, Masterslice Design

6/1971 - 1976

• Bi-Polar and Metal Gate FET Logic and Array Masterslice Design and use of the CDS system. Cell and Image graphic design and chip layout with the CCD and IGS programs running on the 1130/2250 platform. Responsible for requirements for new functions for graphic and checking tools.
• Masterslice design, wireability analysis, cell design, power distribution analysis. Developed good working relationships with many EDS programmers and system people including Ning Nan, Ed Eichelburger, Bill Heller, Al Barone, Lou Biskup and others.
• Masterslice development for use with LDL on a re-map project used as a backup for a mainframe computer. Worked with Al McBride from Los Gatos and John Coleman of Poughkeepsie.

Software Development of diagnostic routines for Electronic Switching System #1.

Awards

• VIM - Outstanding Technical Achievement Award, 12/85
  Attended the Corporate Technical Recognition event in Palm Beach in May, 1986.

• Tusken - Technical Achievement Award

• LDL Network Map print Routine - Informal Award

• LDL Chip Design System Support - Informal Award